The present invention relates generally to RAM memory cells and more specifically to forming the load resistors of the RAM cells.
Area has always been a prime consideration in the formation of integrated circuits especially memory cells since they form a part of an overall matrix. In addition to the surface area needed for the formation of the integrated circuits, or memory cells themselves, the overall layout is also a function of the metallization pattern for the interconnection of the cells to each other and to external circuits. One solution to reduce the surface metallization pattern, is to use the isolation moats as conductors by filling them with metallic material. Typical examples are U.S. Pat. Nos. 3,932,927 and 4,037,306. Similarly, the connection between metallized patterns on both surfaces of the substrate and buried layers using conductive semiconductive material in the isolation moats are illustrated in U.S. Pat. Nos. 3,462,650 and 3,913,124. The connection to buried layers in dielectrically isolated circuits using polycrystalline conductors is illustrated in U.S. Pat. No. 3,858,237.
Although the prior art has recognized the use of the moats in dielectrical isolation as conductors, it has failed to recognize the use of the moats as resistors in an integrated circuit and more specifically as the load resistors in a RAM cell. The prior art generally forms the load resistors of RAM cells as pinched resistors in epitaxial layers or as pinch base resistors. Each of these pinched resistors requires a surface area and thus does not necessarily use space effectively.